spandsp 3.0.0
v80.h
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1/*
2 * SpanDSP - a series of DSP components for telephony
3 *
4 * v80.h - In band DCE control and synchronous data modes for asynchronous DTEs
5 *
6 * Written by Steve Underwood <steveu@coppice.org>
7 *
8 * Copyright (C) 2023 Steve Underwood
9 *
10 * All rights reserved.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU Lesser General Public License version 2.1,
14 * as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*! \file */
27
28/*! \page v80_page The V.80 in band DCE control and synchronous data modes for asynchronous DTEs
29\section v80_page_sec_1 What does it do?
30The V.80 specification defines a procedure for controlling and monitoring the control signals of
31a DCE using in band signals in the data path. It also permits synchronous communication from an
32an asynchronous interface.
33
34\section v80_page_sec_2 How does it work?
35*/
36
37#if !defined(_SPANDSP_V80_H_)
38#define _SPANDSP_V80_H_
39
40enum
41{
42 V80_EM = 0x19,
43
44 /* DTE-to-DCE command definitions */
45 V80_FROM_DTE_MFGEXTEND = 0x20, /* <mfgextend><length><rest of cmd> The DCE shall decode this as a sequence of 3 + (<length> - 1Fh) characters. The meaning of <rest of cmd> is manufacturer specific */
46 V80_FROM_DTE_MFG1 = 0x21, /* The DCE shall decode this as a manufacturer specific command */
47 V80_FROM_DTE_MFG2 = 0x22, /* The DCE shall decode this as a manufacturer specific command */
48 V80_FROM_DTE_MFG3 = 0x23, /* The DCE shall decode this as a manufacturer specific command */
49 V80_FROM_DTE_MFG4 = 0x24, /* The DCE shall decode this as a manufacturer specific command */
50 V80_FROM_DTE_MFG5 = 0x25, /* The DCE shall decode this as a manufacturer specific command */
51 V80_FROM_DTE_MFG6 = 0x26, /* The DCE shall decode this as a manufacturer specific command */
52 V80_FROM_DTE_MFG7 = 0x27, /* The DCE shall decode this as a manufacturer specific command */
53 V80_FROM_DTE_MFG8 = 0x28, /* The DCE shall decode this as a manufacturer specific command */
54 V80_FROM_DTE_MFG9 = 0x29, /* The DCE shall decode this as a manufacturer specific command */
55 V80_FROM_DTE_MFG10 = 0x2A, /* The DCE shall decode this as a manufacturer specific command */
56 V80_FROM_DTE_MFG11 = 0x2B, /* The DCE shall decode this as a manufacturer specific command */
57 V80_FROM_DTE_MFG12 = 0x2C, /* The DCE shall decode this as a manufacturer specific command */
58 V80_FROM_DTE_MFG13 = 0x2D, /* The DCE shall decode this as a manufacturer specific command */
59 V80_FROM_DTE_MFG14 = 0x2E, /* The DCE shall decode this as a manufacturer specific command */
60 V80_FROM_DTE_MFG15 = 0x2F, /* The DCE shall decode this as a manufacturer specific command */
61 V80_FROM_DTE_EXTEND0 = 0x40, /* <extend0><length><rest of cmd> The DCE shall decode this as a sequence of 3 + (<length> - 1Fh) characters; see 7.4 */
62 V80_FROM_DTE_EXTEND1 = 0x41, /* <extend1><length><rest of cmd> The DCE shall decode this as a sequence of 3 + (<length> - 1Fh) characters; see 7.4 */
63 V80_FROM_DTE_CIRCUIT_105_OFF = 0x42, /* Circuit 105 (request to send) is OFF */
64 V80_FROM_DTE_CIRCUIT_105_ON = 0x43, /* Circuit 105 (request to send) is ON */
65 V80_FROM_DTE_CIRCUIT_108_OFF = 0x44, /* Circuit 108 (data terminal ready) is OFF */
66 V80_FROM_DTE_CIRCUIT_108_ON = 0x45, /* Circuit 108 (data terminal ready) is ON */
67 V80_FROM_DTE_CIRCUIT_133_OFF = 0x46, /* Circuit 133 (ready for receiving) is OFF */
68 V80_FROM_DTE_CIRCUIT_133_ON = 0x47, /* Circuit 133 (ready for receiving) is ON */
69 V80_FROM_DTE_SINGLE_EM_P = 0x58, /* The DCE shall decode this as one 0x99 in user data */
70 V80_FROM_DTE_DOUBLE_EM_P = 0x59, /* The DCE shall decode this as 0x99 0x99 in user data */
71 V80_FROM_DTE_FLOW_OFF = 0x5A, /* DCE shall decode this as a command to suspend sending In-Band Commands to the DTE */
72 V80_FROM_DTE_FLOW_ON = 0x5B, /* The DCE shall decode this as permission to resume sending In-Band Commands to the DTE */
73 V80_FROM_DTE_SINGLE_EM = 0x5C, /* The DCE shall decode this as one 0x19 in user data */
74 V80_FROM_DTE_DOUBLE_EM = 0x5D, /* The DCE shall decode this as 0x19 0x19 in user data */
75 V80_FROM_DTE_POLL = 0x5E, /* The DCE shall decode this as a command to deliver a complete set of status commands, one for each circuit or other function supported and enabled. The DCE shall deliver these commands in ascending ordinal order */
76
77 /* DCE-to-DTE command definitions */
78 V80_FROM_DCE_EXTENDMFG = 0x30, /* <extendmfgx><length><rest of cmd> The DCE shall encode this as a sequence of 3 + (<length> - 1Fh) characters. The meaning of <rest of cmd> is manufacturer specific */
79 V80_FROM_DCE_MFG1 = 0x31, /* The DCE shall encode this as a manufacturer specific command */
80 V80_FROM_DCE_MFG2 = 0x32, /* The DCE shall encode this as a manufacturer specific command */
81 V80_FROM_DCE_MFG3 = 0x33, /* The DCE shall encode this as a manufacturer specific command */
82 V80_FROM_DCE_MFG4 = 0x34, /* The DCE shall encode this as a manufacturer specific command */
83 V80_FROM_DCE_MFG5 = 0x35, /* The DCE shall encode this as a manufacturer specific command */
84 V80_FROM_DCE_MFG6 = 0x36, /* The DCE shall encode this as a manufacturer specific command */
85 V80_FROM_DCE_MFG7 = 0x37, /* The DCE shall encode this as a manufacturer specific command */
86 V80_FROM_DCE_MFG8 = 0x38, /* The DCE shall encode this as a manufacturer specific command */
87 V80_FROM_DCE_MFG9 = 0x39, /* The DCE shall encode this as a manufacturer specific command */
88 V80_FROM_DCE_MFG10 = 0x3A, /* The DCE shall encode this as a manufacturer specific command */
89 V80_FROM_DCE_MFG11 = 0x3B, /* The DCE shall encode this as a manufacturer specific command */
90 V80_FROM_DCE_MFG12 = 0x3C, /* The DCE shall encode this as a manufacturer specific command */
91 V80_FROM_DCE_MFG13 = 0x3D, /* The DCE shall encode this as a manufacturer specific command */
92 V80_FROM_DCE_MFG14 = 0x3E, /* The DCE shall encode this as a manufacturer specific command */
93 V80_FROM_DCE_MFG15 = 0x3F, /* The DCE shall encode this as a manufacturer specific command */
94 V80_FROM_DCE_EXTEND0 = 0x60, /* <extend0><length><rest of cmd> The DCE shall encode this as a sequence of 3 + (<length> - 1Fh) characters; see 7.5 */
95 V80_FROM_DCE_EXTEND1 = 0x61, /* <extend1><length><rest of cmd> The DCE shall encode this as a sequence of 3 + (<length> - 1Fh) characters; see 7.5 */
96 V80_FROM_DCE_CIRCUIT_106_OFF = 0x62, /* Circuit 106 (ready for sending) is OFF */
97 V80_FROM_DCE_CIRCUIT_106_ON = 0x63, /* Circuit 106 (ready for sending) is ON */
98 V80_FROM_DCE_CIRCUIT_107_OFF = 0x64, /* Circuit 107 (data set ready) is OFF */
99 V80_FROM_DCE_CIRCUIT_107_ON = 0x65, /* Circuit 107 (data set ready) is ON */
100 V80_FROM_DCE_CIRCUIT_109_OFF = 0x66, /* Circuit 109 (data channel received line signal detector) is OFF */
101 V80_FROM_DCE_CIRCUIT_109_ON = 0x67, /* Circuit 109 (data channel received line signal detector) is ON */
102 V80_FROM_DCE_CIRCUIT_110_OFF = 0x68, /* Circuit 110 is OFF */
103 V80_FROM_DCE_CIRCUIT_110_ON = 0x69, /* Circuit 110 is ON */
104 V80_FROM_DCE_CIRCUIT_125_OFF = 0x6A, /* Circuit 125 (calling indicator) is OFF */
105 V80_FROM_DCE_CIRCUIT_125_ON = 0x6B, /* Circuit 125 (calling indicator) is ON */
106 V80_FROM_DCE_CIRCUIT_132_OFF = 0x6C, /* Circuit 132 (return to non-data mode) is OFF */
107 V80_FROM_DCE_CIRCUIT_132_ON = 0x6D, /* Circuit 132 (return to non-data mode) is ON */
108 V80_FROM_DCE_CIRCUIT_142_OFF = 0x6E, /* Circuit 142 (test indicator) is OFF */
109 V80_FROM_DCE_CIRCUIT_142_ON = 0x6F, /* Circuit 142 (test indicator)is ON */
110 V80_FROM_DCE_SINGLE_EM_P = 0x76, /* The DCE shall encode this as one 0x99 in user data */
111 V80_FROM_DCE_DOUBLE_EM_P = 0x77, /* The DCE shall encode this as 0x99 0x99 in user data */
112 V80_FROM_DCE_OFF_LINE = 0x78, /* Line status is ONLINE (off hook) */
113 V80_FROM_DCE_ON_LINE = 0x79, /* Line status is OFFLINE (on hook) */
114 V80_FROM_DCE_FLOW_OFF = 0x7A, /* The DCE shall encode this as a command to the DTE to suspend sending In-Band Commands to the DCE */
115 V80_FROM_DCE_FLOW_ON = 0x7B, /* The DCE shall encode this as a command to the DTE to resume sending In-Band Commands to the DCE (\*/
116 V80_FROM_DCE_SINGLE_EM = 0x7C, /* The DCE shall encode this as one 0x19 in user data */
117 V80_FROM_DCE_DOUBLE_EM = 0x7D, /* The DCE shall encode this as 0x19 0x19 in user data */
118 V80_FROM_DCE_POLL = 0x7E, /* The DCE shall encode this as a command to the DTE to deliver a complete set of commands, one for each circuit or other function supported by the DTE. Commands shall be delivered in ascending ordinal order */
119
120 /* Synchronous Access Mode In-Band Commands */
121 V80_TRANSPARENCY_T1 = 0x5C, /* Transmit/receive one EM */
122 V80_TRANSPARENCY_T5 = 0x5D, /* Transmit/receive two EMs */
123 V80_TRANSPARENCY_T2 = 0x76, /* Transmit/receive one 0x99 */
124 V80_TRANSPARENCY_T6 = 0x77, /* Transmit/receive two 0x99s */
125 V80_TRANSPARENCY_T3 = 0xA0, /* Transmit/receive DC1 */
126 V80_TRANSPARENCY_T4 = 0xA1, /* Transmit/receive DC3 */
127 V80_TRANSPARENCY_T7 = 0xA2, /* Transmit/receive DC1 DC1 */
128 V80_TRANSPARENCY_T8 = 0xA3, /* Transmit/receive DC3 DC3 */
129 V80_TRANSPARENCY_T9 = 0xA4, /* Transmit/receive EM 0x99 */
130 V80_TRANSPARENCY_T10 = 0xA5, /* Transmit/receive EM DC1 */
131 V80_TRANSPARENCY_T11 = 0xA6, /* Transmit/receive EM DC3 */
132 V80_TRANSPARENCY_T12 = 0xA7, /* Transmit/receive 0x99 EM */
133 V80_TRANSPARENCY_T13 = 0xA8, /* Transmit/receive 0x99 DC1 */
134 V80_TRANSPARENCY_T14 = 0xA9, /* Transmit/receive 0x99 DC3 */
135 V80_TRANSPARENCY_T15 = 0xAA, /* Transmit/receive DC1 EM */
136 V80_TRANSPARENCY_T16 = 0xAB, /* Transmit/receive DC1 0x99 */
137 V80_TRANSPARENCY_T17 = 0xAC, /* Transmit/receive DC1 DC3 */
138 V80_TRANSPARENCY_T18 = 0xAD, /* Transmit/receive DC3 EM */
139 V80_TRANSPARENCY_T19 = 0xAE, /* Transmit/receive DC3 0x99 */
140 V80_TRANSPARENCY_T20 = 0xAF, /* Transmit/receive DC3 DC1 */
141
142 V80_MARK = 0xB0, /* Begin transparent sub-mode HDLC abort detected in framed sub-mode */
143 V80_FLAG = 0xB1, /* Transmit a flag; enter framed sub-mode if currently in Transparent sub-Mode. If enabled, precede with FCS if this follows a non-flag octet sequence Non-flag to flag transition detected. Preceding data was valid frame; FCS valid if CRC checking was enabled */
144 V80_ERR = 0xB2, /* transmit Abort Non-flag to flag transition detected. Preceding data was not a valid frame */
145 V80_HUNT = 0xB3, /* Put receiver in hunt condition not applicable */
146 V80_UNDER = 0xB4, /* not applicable transmit data underrun */
147 V80_TOVER = 0xB5, /* not applicable transmit data overrun */
148 V80_ROVER = 0xB6, /* not applicable receive data overrun */
149 V80_RESUME = 0xB7, /* Resume after transmit underrun or overrun not applicable */
150 V80_BNUM = 0xB8, /* not applicable the following octets, <octnum0 = <octnum1>, specify the number of octets in the transmit data buffer. */
151 V80_UNUM = 0xB9, /* not applicable the following octets, <octnum0 = <octnum1>, specify the number of discarded octets duplex carrier control duplex carrier status */
152 /* Duplex carrier control */
153 V80_EOT = 0xBA, /* Terminate carrier, return to command state loss of carrier detected, return to command state */
154 V80_ECS = 0xBB, /* Go to on-line command state confirmation of EM esc = command */
155 V80_RRN = 0xBC, /* Request rate reneg. (duplex) indicate rate reneg. (duplex) */
156 V80_RTN = 0xBD, /* Request rate retrain (duplex) indicate rate retrain (duplex) */
157 V80_RATE = 0xBE, /* Following octets, <tx = <rx>, set max. tx and rx rates retrain/reneg. completed; following octets, <tx><rx>, indicate tx and rx rates V.34 HD carrier control V.34 HD duplex carrier status */
158 /* V.34 HD carrier control */
159 V80_PRI = 0xBC, /* Go to primary ch. operation pri. ch. operation commenced; following octet, <prate>, indicates bit rate */
160 V80_CTL = 0xBF, /* Go to control ch. operation ctl. ch. operation commenced; following octets, <prate><crate>, indicates bit rates */
161 V80_RTNH = 0xBD, /* Initiate pri. channel retrain indicate pri. channel retrain */
162 V80_RTNC = 0xC0, /* Initiate ctl. channel retrain indicate ctl. channel retrain */
163 V80_RATEH = 0xBE, /* Following octets, <maxp = <prefc>, set max. pri, rate and preferred ctl. ch. rate not applicable */
164 V80_EOTH = 0xBA, /* Terminate carrier carrier termination detected */
165 //V80_ECS = 0xBB /* Go to command state not applicable */
166};
167
168/* Primary channel data signalling rate codes */
169enum
170{
171 V80_BIT_RATE_1200 = 0x20,
172 V80_BIT_RATE_2400 = 0x21,
173 V80_BIT_RATE_4800 = 0x22,
174 V80_BIT_RATE_7200 = 0x23,
175 V80_BIT_RATE_9600 = 0x24,
176 V80_BIT_RATE_12000 = 0x25,
177 V80_BIT_RATE_16800 = 0x27,
178 V80_BIT_RATE_19200 = 0x28,
179 V80_BIT_RATE_21600 = 0x29,
180 V80_BIT_RATE_24000 = 0x2A,
181 V80_BIT_RATE_26400 = 0x2B,
182 V80_BIT_RATE_28800 = 0x2C,
183 V80_BIT_RATE_31200 = 0x2D,
184 V80_BIT_RATE_33600 = 0x2E,
185 V80_BIT_RATE_32000 = 0x2F,
186 V80_BIT_RATE_56000 = 0x30,
187 V80_BIT_RATE_64000 = 0x31
188};
189
190typedef struct v80_state_s v80_state_t;
191
192#if defined(__cplusplus)
193extern "C"
194{
195#endif
196
197SPAN_DECLARE(const char *) v80_escape_to_str(int esc);
198
199SPAN_DECLARE(int) v80_bit_rate_code_to_bit_rate(int rate_code);
200
201#if defined(__cplusplus)
202}
203#endif
204
205#endif
206/*- End of file ------------------------------------------------------------*/
Definition private/v80.h:30